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Parasitic extraction
Results: 29

#	Item
21	White Paper Design Solutions for 20nm and Beyond June 2012 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:41:40 Multiple patterning Signoff Design rule checking Standard cell Parasitic extraction Physical design Application-specific integrated circuit Synopsys Integrated circuit design Electronic engineering Electronic design automation Integrated circuits
22	Datasheet NanoTime Transistor-level Static Timing Analysis Solution for Custom Designs Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-27 00:06:11 Signoff Synopsys Static timing analysis Signal integrity Electronic circuit simulation Delay calculation Logic simulation Parasitic extraction SPICE Electronic engineering Electronic design automation Digital electronics
23	Datasheet StarRC Parasitic extraction Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 15:15:32 Integrated circuits Electronic design Parasitic extraction Electromagnetic field solver Standard cell Circuit extraction Application-specific integrated circuit Signoff Synopsys Electronic engineering Electronic design automation Electronics
24	Datasheet StarRC Custom Parasitic extraction for next-generation custom IC design Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:39
25	PROJECT PROFILE 2A704: Robust design for efficient use of nanometre technologies (ROBIN) EDA FOR SOC DESIGN AND DFM Add to Reading List Source URL: www.catrene.org Language: English - Date: 2009-03-25 10:35:46 Electronic design Integrated circuits Digital electronics Signal integrity Static timing analysis System on a chip Parasitic extraction Electronic circuit MOS Technology SID Electronic engineering Electronics Electronic design automation
26	Solution Overview Custom and Mixed-Signal Design Solution Unified Solution for Custom and Cell-Based Design and Verification January 2012 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:28:38 Signoff Synopsys Waveform viewer Standard cell Design rule checking Physical design Electronic circuit simulation Parasitic extraction SystemVerilog Electronic engineering Electronic design automation Digital electronics
27	The World Leader in High Performance Signal Processing Solutions TAU Workshop 2014 Increasing the Accuracy of Interconnect Derates: A Path Based Method Ryan Kinnerk, Dr. Emanuel Popovici, Colm O’Doherty Add to Reading List Source URL: tauworkshop.com Language: English - Date: 2014-04-28 21:47:41 Electronic design automation Signoff Parasitic extraction
28	2003 Workshop on Compact Modeling Unified RLC Model for On-Chip Interconnects Sang-Pil Sim and Cary Y. Yang Microelectronics Lab., Santa Clara University, CA, Add to Reading List Source URL: www.nsti.org Language: English - Date: 2010-03-19 15:29:00 Electronic design automation Integrated circuits Capacitance Electricity Electromagnetic field solver Parasitic extraction Electromagnetism Electronic engineering Electronics
29	MODELING AND SCREENING ON-CHIP INTERCONNECT INDUCTANCE a dissertation submitted to the department of electrical engineering and the committee on graduate studies Add to Reading List Source URL: marco.stanford.edu Language: English - Date: 2004-08-27 14:43:22 Electrodynamics Energy storage Parasitic extraction Electronic design Inductance Integrated circuits RCX Parasitic element Capacitor Electronic engineering Electronics Electromagnetism